Efficient Hardware Fault Tolerance Using Field-programmable Gate Arrays

EEcient use of redundant computing resources is desirable in fault tolerance. To meet its fault tolerance requirements, a task may need all the computing modules; but when a lesser amount of fault tolerance is suucient, then multiple tasks should be allowed to execute concurrently. Systems supporting this type of operation usually have their fault tolerance controlled by software. Fault tolerance control based on Field-Programmable Gate Arrays (FPGAs) shows promise of performance gains over software based approaches. Dynamic FPGA reconnguration supports, in hardware, eecient fault tolerance among a collection of computing modules. Tasks not requiring fault-tolerant operation are given uniprocessing or multiprocessing support. The FPGA is designed so that it needs, at most, only partial reconnguration when switching between its system services.